library verilog;
use verilog.vl_types.all;
entity alu is
    port(
        op1             : in     vl_logic_vector(15 downto 0);
        op2             : in     vl_logic_vector(15 downto 0);
        aluctr          : in     vl_logic_vector(3 downto 0);
        \out\           : out    vl_logic_vector(15 downto 0);
        carry_out       : out    vl_logic;
        zero            : out    vl_logic
    );
end alu;
